Every chatbot that still remembers what was said three questions ago is keeping notes, and those notes have quietly turned into a storage problem. Panmnesia, a fabless chip company in Daejeon, South Korea, says early access partners can now request pre-release silicon and pilot systems of its PCIe 6.4-CXL 3.2 fusion switch, a part built to give the notes somewhere fast to live.
Two acronyms first, then the argument. A switch is the interchange connecting the pieces of a rack, the CPUs and GPUs and memory boxes, so they reach each other without detouring through a general-purpose network. CXL, said letter by letter as see ex ell, is Compute Express Link, a standard for wiring those pieces together so a machine can add only the resource it has run short of.
The notes have a name: the KV cache, short for key-value cache. A model stores intermediate results there and reads them back instead of recomputing them, which is the difference between looking up a phone number once and looking it up again on every call. Agentic systems, which loop through a task rather than answering once and stopping, pile up far more of it.
That is where Panmnesia locates the bottleneck. Once the cache outgrows GPU memory, the usual fix is to park it in external memory or storage reached over Ethernet, InfiniBand or a storage interface, and the round trip burns time the accelerators spend waiting. The company proposes a CXL memory pool instead, which it says allows direct memory access without software intervention.
Port-based routing is the specification detail the pitch keeps returning to. Conventional PCIe routing arranges devices in a tree with the CPU at the root; port-based routing lets switches and devices be wired in whatever shape the workload wants, and lets two devices trade data directly with minimal CPU involvement. Panmnesia says it is the only company offering a switch chip that supports it, and names no outside party that has verified that.
For anyone keeping score on specifications, the chip carries all three CXL sub-protocols, CXL.cache, CXL.mem and CXL.io, and supports PCIe Gen 6 signalling at 64 gigatransfers per second. Switches can also be cascaded, so thousands of devices across several racks present themselves as one fabric.
The controller underneath is the company's own design, and that, rather than the protocol checklist, is what it treats as the real differentiator. Chief executive Myoungsoo Jung said this in Panmnesia's account of its ISPASS 2026 keynote on April 28: "Because we develop our controllers and IP in-house, we can rapidly deliver customer-tailored solutions." Latency for that controller is put in double-digit nanoseconds, a figure that arrives without a named third-party benchmark.
Money and partners fill in the rest. The company says it raised roughly $60 million in a Series A in 2024 at a valuation of about $250 million, and The Elec reports it intends to show an AI server rack built with SK Telecom before the year is out.
Pre-release silicon is not a shipping product, and an interconnect claim only means much once somebody outside the company measures it. If that rack demonstration lands, it would be the first outside look at whether the notepad really did get closer to the model.
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