Siemens has expanded its collaboration with TSMC to hand one of the least glamorous jobs in chip design over to software agents: finding the layout violations that would stop a design from being manufacturable, and then fixing them.
Every chip layout has to obey a rulebook written by the factory that will build it. Spacing here, wire width there, thousands of rules deep, and a large modern layout can break them in tens of thousands of places at once. The software that hunts for those breaks is called Design Rule Check, said letter by letter as DRC, and it is the world's fussiest proofreader. Traditionally it flags the mistakes and leaves a human to correct them, one at a time, for weeks.
The fixing part is what Siemens and TSMC are now automating, inside the Fuse EDA AI System that Siemens describes as "a comprehensive domain-scoped agentic AI system for semiconductor". The two companies are using it to drive multi-step, multi-tool automations for DRC-centric physical verification in Calibre, Siemens' long-established sign-off tool, and to feed designers guided recommendations and real-time command execution in the Aprisa digital implementation software.
"By combining our AI innovations with TSMC’s leading-edge process technologies, we’re helping customers reach new levels of speed, accuracy and design confidence," said Ankur Gupta, executive vice president, EDA IC Software, Siemens Digital Industries Software.
What that sentence does not contain is a number. No benchmark is offered for how much faster an automated fix is than a human one, no methodology is described, and no customer is named as having run the flow on a production design. Anyone weighing the claim is weighing a description of a capability rather than a measurement of one.
Quieter, and arguably more useful, is the certification half of the announcement. Siemens says its Calibre nmPlatform software is now certified for TSMC's 3nm, 2nm, A16 and A14 process technologies, its Solido Simulation Suite is certified for SPICE accuracy on N3A, N2P, A16 and A14, its mPower analog tool is certified for transistor-level EM/IR sign-off on N2P, and Aprisa has picked up TSMC N2P Integrated Tool Certification.
Certification sounds like paperwork. In practice it decides whether a design team can start work on a node at all, because a fab will not accept a tapeout verified by a tool it has not signed off, and the tool vendor cannot write the rule decks without the fab's cooperation. The AI agents are the headline; the certifications are the permission slip.
Aveek Sarkar, director of the ecosystem and alliance management division at TSMC, framed the work as ecosystem plumbing. "TSMC greatly values our longstanding partnership with Siemens, a key member of our Open Innovation Platform® (OIP) ecosystem, as we work together to enable next generation semiconductor designs," he said.
A third strand matters to anyone stacking chips rather than shrinking them. Calibre 3DStack supports interface checks, inter-chiplet DRC on interposers, antenna analysis and point-to-point resistance extraction for TSMC's 3DFabric packaging, all expressed in the 3Dblox syntax, and Calibre 3DThermal has been certified by TSMC for both static and transient thermal analysis. Siemens also lists flow development for TSMC's Compact Universal Photonic Engine, the packaging technology that seats optics beside logic.
Stack four dies and the heat stops escaping the way a simulator built for flat chips assumes it will, which is why thermal sign-off has quietly turned into a verification problem rather than a packaging afterthought. Siemens is betting that the tedious middle of chip design, the part nobody frames a press release around, is where AI earns its keep.
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