The hardware behind the future


NAND the Gap: TechInsights’ New Briefing Lands While Its Public Teardown Record Trails the 300-Layer Era

The teardown house’s subscriber NAND briefing arrives while the freshest flash analysis it leaves in public view is a 128-layer part, from an era its own 300-layer outlook has left behind.

NAND the Gap: TechInsights’ New Briefing Lands While Its Public Teardown Record Trails the 300-Layer Era

TechInsights has released the first NAND installment of its 2026 Advanced Memory Essentials briefing series, and the material the teardown house leaves in public view tells a story of its own about where flash analysis now lives.

The subscriber package sits behind the platform login, in the same slides-and-video format as its DRAM sibling. What the firm says in the open is blunter. Its 2026 Memory Outlook states that "3D NAND surpasses 300 layers with wafer bonding and hybrid stacking." Decoded, the layer-count race that defined a decade of flash marketing has handed the baton to packaging, and the hard engineering now happens where two wafers meet.

Eight manufacturers populate the firm's public NAND roadmap: Samsung, SK hynix, Micron, Solidigm, Kioxia, Western Digital, YMTC and MXIC. The page promises that "Upcoming new and advanced 3D NAND technologies including multi-stacking, hybrid bonding, and package solutions are also described on the roadmap." That is the entire supplier universe for the storage the AI buildout depends on, which goes some way to explaining why close analysis of it commands subscription pricing.

Set against that 300-layer present, a NAND teardown the firm does leave in open view is its analysis of the SK hynix 128-layer part, the one branded 4D NAND. "SK hynix has released the world's first 128-layer (128L) 3D NAND, which they have termed 4D NAND," the write-up opens, in a sentence that dates itself.

The archived numbers still reward a close read. The die runs 147 gates to deliver 128 active wordlines, with 9 dummy wordlines, 7 select gates on the source side and 3 on the drain side, for a vertical cell efficiency of 87.1 percent and a TLC bit density TechInsights puts around 8.15 gigabits per square millimetre. Its periphery-under-cell construction, the second PUC generation after the 96-layer part, is the same architectural idea Micron and Intel call CuA and YMTC executes as Xtacking, with the logic tucked beneath the array instead of beside it.

That distance between the open record and the login material spans more than two product generations, and it is not an accident. Teardown economics run on subscribers, and the outlook page states the terms plainly: "To view any 2026 Outlook Report, you must be a registered TechInsights Platform user." Anyone doing supplier diligence on current flash is working from purchased slides, vendor claims, or archaeology. If the firm's own headline holds and the action has moved to bonded interfaces, the most consequential NAND engineering of this cycle is also the least publicly documented in years.

Bootnote. The fourth dimension in 4D NAND is marketing, not geometry. The term is SK hynix branding for periphery-under-cell construction, the same family as Micron's CuA and YMTC's Xtacking, and the industry has never settled on a vendor-neutral name for it. The layers multiplied; the dimensions did not.

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