Sandisk and SK hynix have published the first open technical specification for High Bandwidth Flash through the Open Compute Project, six months after the two companies launched the consortium meant to turn the technology into an industry standard.
HBF stacks NAND dies and presents them to an accelerator the way HBM presents DRAM. The published figures run to 512GB in a dual stack built from 8-high and 16-high dies, with three bandwidth grades spanning roughly 0.4TB/s to 3.0TB/s and UCIe as the interconnect. At the top grade that is HBM-class bandwidth attached to NAND-class capacity, which is the whole pitch: inference workloads want the model resident, and DRAM residency is what breaks the budget.
The document itself covers the xPU host interface, electrical characteristics, reliability and packaging guidance for the die stack, and a software guide for reads and writes. That is enough for a system architect to design around. It is not enough to procure. No HBF part has a sample date, a price, or a named GPU platform in either company's release.
Alper Ilkbahar, Sandisk's chief technology officer, frames the release as groundwork for what follows: "This specification helps give system designers a practical path to bring high-capacity, high-bandwidth memory closer to compute, while enabling more flexible architectures." He also calls it a milestone for "AI systems built to improve token economics at scale." Translated, tokens per dollar decide whether inference is a business, memory sits at the top of that cost stack, and the company that owns the middle tier owns the lever.
The plumbing version comes from Kim Chun-sung, executive vice president and head of solution development at SK hynix: "Through HBF, SK hynix will expand the boundaries between memory and storage and contribute to building new architectures that enhance overall system efficiency." The boundary talk matters. A working HBF tier would take traffic that currently bounces between HBM and SSDs and give it a home with its own interface, its own packaging rules, and its own failure modes.
Publishing through OCP, with Google and Tenstorrent named as consortium members doing validation work, is the standards play in plain view. An open specification invites the ecosystem to design sockets before silicon exists, and it crowds out proprietary alternatives by making the open one the default. The releases name no other accelerator vendor, and the companies that ship most AI accelerators are absent from the member list as published.
Alongside the spec, SK hynix showed its V10 NAND publicly for the first time, a 375-layer 4D part the company says delivers 2.5 times the performance per watt of the previous generation. The figure is the vendor's own, with no benchmark or methodology published beside it. Enterprise SSDs on V10 are planned for mass production in early 2027, which for now makes V10, not HBF, the piece of this announcement with a date attached.
Bootnote: HBF has moved quickly by memory-standards pace. Sandisk and SK hynix agreed to joint standardization in August 2025, formed the consortium in February 2026, and published this first specification at the Future of Memory and Storage show in Santa Clara roughly six months after that. A specification without silicon is still paper, but paper that arrives first tends to be what the sockets get designed around.
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