Renesas has built a configurable ternary content-addressable memory on a 3nm FinFET process and presented the results at the International Solid-State Circuits Conference in San Francisco, held from February 15 to 19.
The number the company leads with is density. Renesas puts the macro at 5.27 megabits per square millimeter and calls that industry leading. No prior part is named, no competitor is named, and no measurement conditions are given, which makes the superlative unfalsifiable as published.
How it got there is more interesting than the claim. Hard macros come out of a memory compiler at fine granularity, with search key widths from 8 to 64 bits and entry depths from 32 to 128, and larger arrangements such as 256 bits by 4,096 entries are assembled by pairing those macros with tool-generated soft macros in one configurable block. Scaling with hard macros alone adds banks and repeaters, inflates peripheral area and makes timing closure harder as the array grows.
Energy is where the conditions matter most. Renesas cites search energy reductions of up to 71.1 percent for a column-wise pipelined search and up to 65.3 percent for a row-wise one. Read the qualifiers. The 71.1 percent figure applies only with key partitioning and keys longer than 64 bits, the 65.3 percent figure only without partitioning and keys of 64 bits or fewer, and both are quoted for configurations between 64 and 256 bits wide by 512 entries deep. These are reductions against Renesas's own unpipelined search, not against anybody else's TCAM.
The mechanism is a two-stage search with an all-mismatch detection circuit in front. Stage one determines whether every entry misses, and stage two halts if it does. That makes the saving data dependent by construction: a workload where most searches find nothing gets the full benefit, and one that keeps hitting cannot skip the second stage anywhere near as often.
Point measurements come in at 0.167 femtojoules per bit of search energy and a 1.7 GHz search clock, both quoted for a 256 bit by 512 entry configuration. That is one eighth the depth of the 256 bits by 4,096 entries the same release cites as the configuration 5G and edge traffic now demand.
Also reported is a figure of merit of 53.8, defined in the release as density multiplied by speed divided by energy, said to exceed prior work that is never named. A metric multiplying the two things a design team optimized and dividing by the one it cut will travel a long way on modest movement in each.
The functional safety work is what earns the automotive framing. TCAM bitcells holding one address sit physically adjacent, so a single soft error event can flip two bits in the same word, and conventional single error correction with double error detection cannot fix that. Renesas splits odd and even data buses across user data and ECC parity to push the cells apart, turning would-be double-bit errors into correctable single-bit ones, and moves parity into a dedicated SRAM with an address decoder independent of the TCAM so a write to the wrong TCAM address becomes detectable. That is a layout and architecture answer, not a process one.
What the release does not carry is a product. There is no part number, no customer, no sampling or qualification date, no ASIL level claimed against ISO 26262, and no coverage percentage behind the phrase about significantly improved safety coverage. A test chip and a conference paper exist; the automotive silicon using either remains hypothetical.
Bootnote. A TCAM compares a search key against every stored entry at once and returns the address of the match, which is why routers have used them for decades to do longest-prefix lookups at line rate. The ternary part is a third state alongside one and zero, a don't-care bit letting a single entry match a whole range of keys. The price has always been power and area, because every cell participates in every search, which is exactly the bill being cut here.
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