CXMT has started mass production on its fifth-generation DRAM platform, G5, and says two 24Gb LPDDR5X dies built on it are already in volume production, announced at the World Manufacturing Convention in Hefei.
The figures come from CXMT's own Chinese-language posting, whose footnote says the half-pitch, aspect ratio and cell height are measured on actual product with normal measurement deviation, and that the dies-per-wafer comparison is normalized to an 8Gb die. The active-area half-pitch in the memory array is 11.95 nanometers, reached with quadruple patterning. The storage capacitor has an aspect ratio of 45:1. The core functional area of the cell stands 6,762 nanometers tall, which CXMT credits to a high-k metal gate process adapted for DRAM.
Half-pitch is one dimension of one structure, not a node. Samsung, SK hynix and Micron label their volume nodes 1b and 1c, names that do not correspond to a single measured feature, so 11.95nm cannot be laid directly against them. Electronics Weekly sets CXMT's number against the IEEE's International Roadmap for Devices and Systems, which puts the half-pitch at 10nm on the current 2nm DRAM node and 8nm on the 1nm node due in 2027 or 2028. On that yardstick G5 sits roughly one node behind the roadmap's current entry.
The density claim is the one to read carefully. CXMT says G5 produces at least 50 percent more dies per wafer than its fourth-generation platform, and the 24Gb LPDDR5X parts hold 50 percent more than the same-type parts they replace. Both comparisons are against CXMT's own previous products, not against anyone else's, and dies per wafer is a gross count taken before yield. The announcement gives no yield, no wafer output and no ramp schedule, so the 50 percent says where CXMT's cost per bit went relative to its own last node, not where it sits against Micron's.
One carrier overstates it. The Register's Asia round-up reads the announcement as essentially doubling memory density, meaning twice the dies from a wafer. CXMT's own text says at least 50 percent more, and the issuer's number is the one to hold onto.
The two products are 24Gb per die in 496-ball and 245-ball packages, for mid-to-high-end phones and portable electronics, and CXMT says both have reached volume production. The same news page carries the company's earlier claim that its LPDDR6, a 16Gb die rated at 12,800Mbps, is in mass production and shipping in Xiaomi's 18 Fold, so G5 is the second production milestone on that page.
Vice president Luo Xiaodong told the convention that the company's process capability is now on par with the industry's most advanced mass-produced nodes, in Electronics Weekly's rendering of remarks he gave in Chinese. On par is a process claim, not a share claim. TrendForce's public second-quarter DRAM revenue ranking gives Samsung 39.4 percent, SK hynix 24.9 percent and Micron 23.3 percent, which is 87.6 percent between them, and names Nanya, Winbond and PSMC below them without listing CXMT at all. The 9.5 percent share attributed to CXMT for that quarter reaches English-language readers through Seoul Economic Daily, which relays it from TrendForce in an AI-translated report, so it is a carried figure rather than one from TrendForce's public release.
The same TrendForce release says the incumbents' inventories sit at historic lows with additional supply allocated mainly to servers, which is the market G5 walks into. If the yields behind these numbers are real, the phone and PC makers the big three have been rationing get a fourth supplier at something close to a current node, and that is the corner of the DRAM market where price relief would show up first.
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