Samsung Electronics used the Memory Executive Summit ahead of SEMICON Taiwan to attach numbers to the memory roadmap it has been previewing all summer, with HBM5 targeted at twice the performance of HBM4E, zHBM at eight times, and zNAND-O due to sample in 2028, according to reporting by the Korea Herald and the Korea Times. Samsung is selling the whole package under one label.
That label is CUBE, for capacity, utilization, bandwidth and efficiency, and Choi Jang-seok, who heads memory product planning, carried it through the Taipei keynote. The Korea Herald reports him arguing that vertical stacking lifts capacity without growing the board footprint, that the value of 3D lies in how each layer is used, and that shorter die-to-die distances raise bandwidth. The stated end goal, per both papers, is less energy per bit moved.
The HBM5 figures are the near-term ones. Both papers report targets of double HBM4E's performance, 20 percent better performance per watt and 20 percent lower thermal resistance, and the Korea Times adds that HBM4E is in sample testing at major customers. Thermal resistance is the number to watch. HBM4 already pushed Samsung's base die onto a 4nm logic process largely to hold power down, as Sangwook Han of its DRAM design team set out at Hot Chips in a talk written up by Tom's Hardware, and every added die lengthens the heat path.
zHBM is where the baseline needs reading twice. Samsung's own release from the Future of Memory and Storage show in August states: "A next-generation interface system incorporating zHBM is expected to deliver approximately eight times the performance of HBM5." In Taipei, as reported by both papers, the same eightfold figure was set against HBM4E, alongside triple the performance per watt and a 75 to 90 percent cut in thermal resistance. The multiplier held and the generation it is measured against moved back one. Since HBM5 is itself pitched at twice HBM4E, the two statements differ by roughly a factor of two on the headline number, and neither paper addresses the gap. Whether Samsung restated its model or a baseline was lost in translation is unknown.
What zHBM is has not changed since Hot Chips. Tom's Hardware's write-up of Han's talk describes the third phase of a base-die roadmap: the processor sits directly beneath the DRAM stack, the edge PHY gives way to distributed I/Os, and Samsung's projections cut I/O power by around 70 percent against HBM5 while holding stacks to roughly four high because of heat. Han gave no launch timeline, and the Taipei accounts give none for zHBM either.
zNAND-O is the one item with a date. The Korea Times describes four or eight V-NAND dies stacked with TSVs, targeting seven times the read bandwidth and power efficiency of conventional NAND, with sampling scheduled to begin in 2028; the Korea Herald adds a target of ten times the bit density of DRAM. That last figure says what is being sold: a capacity tier positioned against DRAM on density rather than against flash on speed.
One phrase recurs in both the August release and the Taipei coverage: customer-specific IP integrated into an interlayer between memory and accelerator. Decoded, the base die is becoming the product. Samsung's memory division is offering foundry-style customization under a standard DRAM stack, and the Hot Chips phases, custom HBM first and full 3D last, are the order in which it expects to get paid for it.
Bootnote: the August release also pegs zHBM at more than ten times the memory density of HBM5 through wafer bonding, a figure the Taipei coverage did not repeat.
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